1. Field of Invention
This invention relates in general to the fabrication of integrated circuits, and more particularly to a fabricating method for static random-access-memory (SRAM) eligible for dimensional reduction and producing a higher level of integration.
2. Description of Related Art
SRAMs are now widely used inside many integrated circuit devices, particularly in the telecommunication and electronic industries. Therefore, how to miniaturize and how to increase the level of integration while maintaining device quality is the foremost goal for future development. Polysilicon load (or polyload) is one of the devices in a SRAM unit cell. The polyload functions as a resistor and is generally formed by lightly doping (or not doping at all) ions into a specific section of the polysilicon layer, while the other sections of the same polysilicon layer are more heavily doped to form the interconnects.
A circuit diagram for a conventional SRAM unit is shown in FIG. 1. Devices of a SRAM unit include two polyloads R1 and R2, two pull-down transistor Q1 and Q2, two pass transistors Q3 and Q4. Transistors Q1,Q2,Q3 and Q4 utilize a first polysilicon layer (poly1) as their gate terminals, and a second polysilicon layer (poly2) with the higher resistance sections serving as their polyloads and the lower resistance sections as their interconnects. Conventional fabricating techniques use the same polysilicon layer (poly2) for both the polyloads and the interconnects. Those sections designed to be the interconnects are heavily doped while the sections that serves as the polyloads are either lightly doped or simply not doped at all. The interconnects and the polyloads together constitute an electrical pathway for linking up a voltage source Vcc to node points A and B. Since the same polysilicon layer (poly2) is used for interconnects and polyloads in the conventional fabricating method, at least two doping operations are required.
To better understand the steps involved and the disadvantages of the conventional method for fabricating a SRAM polyload, an example is provided below.
FIG. 2 is a cross-sectional view showing the structure of a SRAM polyload formed by a conventional method. Referring to FIG. 2, the fabricating method first involves forming a polysilicon gate device 12 and a polysilicon voltage source line device 14 above a silicon substrate 10, and then depositing an insulating layer 16 on top, followed by etching the insulating layer 16 to form respectively a contact window 17a exposing the polysilicon gate device 12 below as well as another contact window 17b exposing the polysilicon voltage source line device 14 below. Next, a polysilicon layer covering the insulating layer 16, also filling up the contact windows 17a and 17b is formed. In the subsequent processing, section labelled 18 is lightly doped to act as a polyload region, while sections 20a and 20b are more heavily doped in a second doping operation to form the interconnect regions.
One major disadvantages of the SRAM polyload fabricated by the above conventional method is the necessity to take into consideration the lateral diffusion length of ions in the polysilicon layer, for example, about 1.5 .mu.m, and so when further dimensional reduction for memory units are desired, ionic diffusion definitely sets a limit on the control of product quality. Furthermore, due to an uneven topography of the underlying layer, two adjacent polyloads produced alongside each other may be unsymmetrical, and as a result of such errors, may lead to a lack of stability for the memory units, and in more serious cases, may even affect device functioning.